7/14/2026 at 7:35:56 AM
The graphs are beautiful, however they're independent of the language (because they're a visualization of the resulting gates). You could get the same graphs from VHDL or Verilog.I don't like the "fallback" mechanism, because it will be used when "something goes wrong", without being specific about exactly under what conditions should the fallback happen. Maybe I made a mistake, "something" fails at a step I didn't expect, and this will silently implement in a way I didn't mean (maybe the result is even correct, just using way more gates than needed).
by lefra