4/9/2026 at 8:02:42 PM
I had been pondering about doing more or less the same thing for 6502 (6510).It was always the dilemma of whether to pull the CPU out of a C64 and replace it like this, do it as a bus mastering cartridge, or replace the RAM.
I have been leaning towards the cartridge plan to avoid the requirement of doing machine surgery. If you get the RP2350 to pretend to be the RAM then the video hardware could read directly out of it which makes all sorts of shenanigans possible (every line a BADLINE).
At some point it would look like just plugging A VIC-II and a SID into a board with the RP2350 though, The cartridge approach means you have to do transfers across into the computer's RAM, but you could also write to hardware registers every CPU cycle, which would enable some potentially new modes that would not be entirely dissimilar to every line a BADLINE.
Right now I'm mucking around with getting the RP2350 to output video constructed a scanline at a time, using as little CPU as possible. I got three layers of tiles and two layers of sprites each with different pixel formats working yesterday. Quite pleased with that. The CPU calculates a handful of values per scanline, but fetching tilemap data, then tile data, then conversion to pixel values, transparency and palette lookup are all DMA and PIO. Does 1,2,4, and 8 bits per pixel, each tile/sprite/imagebuffer layer with independent 24 bit palettes.
by Lerc
4/10/2026 at 4:41:16 AM
> I had been pondering about doing more or less the same thing for 6502 (6510).https://microcorelabs.com/2025/12/15/worlds-fastest-commodor...
https://microcorelabs.com/2021/01/08/mcl65-worlds-fastest-ap...
by musicale
4/9/2026 at 8:13:02 PM
You have such ponderings in common with engineers@work:"and palette lookup are all DMA and PIO"
PIO is a revelation.
by topspin
4/9/2026 at 10:10:24 PM
It's great, but I think the critique from the other day was also pretty valid. and offered an alternative.https://www.bunniestudios.com/blog/2026/bio-the-bao-i-o-copr...
I think, for my use, just having the ability to write to DMA registers would have been a big advantage. It feels wasteful to have A DMA waiting on a FIFO just to write what it gets to DMA registers to do the transfer you actually wanted.
Looking at the Architecture diagram It seems like it could have allowed that and stayed on the same side of the AHB5 splitter.
by Lerc
4/9/2026 at 9:45:42 PM
I do love the PIO. I want to show it to a computer engineer from the 80s.by teaearlgraycold
4/9/2026 at 10:22:37 PM
Not all that different from the MCS-96 HSIO.by zeckalpha