It looks like the FPGA that monitors/controls the redundant/lockstep CPUs might be radiation tolerant. From [0]:"..the critical FPGA which is always on for the duration of the mission, the radiation tolerant ProASIC3 is chosen with the military temperature grade (-55 C to 125 C) and -1 speed grade to mitigate the degradation in the propagation delay caused by the total dose radiation. The single-event upset (SEU) is mitigated with triple module redundancy (TMR) in the FPGA design.
...
The FPGA device is a military-grade version of MicroSemi’s ProASIC3L, which uses the same silicon as the radiation-tolerant device from the same family."[0]
The specs from [1] say there is also a specific radiation-tolerant variant.
So it looks like the CPUs themselves have dual lock-stepped cores, and the CPU checks for errors each cycle. If there's an error it flags the FPGA, which switches to the other CPU.
[0] https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_A...
[1] https://ww1.microchip.com/downloads/aemDocuments/documents/F...