alt.hn

4/20/2025 at 1:13:41 AM

Subnanosecond Flash Memory

 https://www.nature.com/articles/s41586-025-08839-w

by thund

4/23/2025 at 7:17:33 AM

to demonstrate that the device remains stable even after 60,000s

A little over 16 hours? That's suspiciously short. The endurance vs retention curve isn't clear from this article either; they say "10 years" and "5.5 million cycles" but it seems more like you either get 10 years and 1 cycle, or 5.5M cycles to immediate failure with no regard to retention.

It reminds me of this old paper on testing USB drives for endurance, where they just hammered at the flash until it failed to program immediately and "concluded" that the endurance was many orders of magnitude higher than the manufacturer's specifications, with no attention paid to retention at all: https://www.usenix.org/event/fast10/tech/full_papers/boboila...

by userbinator

4/25/2025 at 9:33:14 PM

That would be perfect for any high performance working storage on replicated distributed applications. Stuff like Redis, Cassandra, etc... You would never turn off the power anyways. Places where you are otherwise using RAM disk or TMPFS storage.

by foxyv

4/23/2025 at 9:01:57 AM

It's more like DRAM with a much longer refresh time (60 ks instead of 60 ms).

by tlb

4/23/2025 at 1:58:11 PM

60,000 seconds was the amount of time it was tested for, they then extrapolate that out linearly. It doesn't need refreshing that often.

by IanCal

4/23/2025 at 3:00:11 PM

> 60,000 seconds was the amount of time it was tested for,

Surely if they already have a test setup, then having a test last for 600,000 seconds isn't very hard?

Things that look linear for a short period end up being exponential over longer periods. I don't think we can assume linear extrapolation here. There could be physics at play where exponential degeneration of the voltage occurs.

Its a good start of a test. But it seems weird in that a paper like this would have taken much more than ~1 week to write, so making a test last ~1 week for their calculations seems within the feasibility of this group. But its oddly missing data.

by dragontamer

4/23/2025 at 2:31:37 PM

DRAM will also normally hold most of its data for 1000x longer than the rated (usually 60 ms) refresh time. This has sometimes been used to recover secrets from powered down computers. The rated refresh time is chosen to give near-zero errors over years of operation, accounting for worse-case leakage from any bit, but most bits leak much less than that.

by tlb

4/23/2025 at 6:40:09 PM

I think older systems also tended to use a fixed refresh rate, rather than refreshing more often as the DRAM temperature rises. Temperature sensors on DRAM are more common now, so systems don't have to be so conservative with the refresh intervals.

by wtallis

4/23/2025 at 2:14:10 PM

Even if it did have a 16 hour retention, this memory would have plenty of uses.

Adding a couple of percent of ECC data tends to 10x retention anyway, so there is a direct engineering trade off between retention and capacity.

by londons_explore

4/23/2025 at 9:13:27 AM

Assume the memory is instant. We still need to communicate with it across physical distance. How far away the memories are in space is way more critical than the speed of any one element in isolation.

Why are we constrained to such a relatively small amount of L1 cache? What would stop us from extending this arbitrarily?

by bob1029

4/23/2025 at 11:57:10 AM

HP was the only CPU vendor I recall that went for massive L1 with their PA-RISC chips, some with 1-2MB of L1. I'm going to say a large L1 is ~1MB for this comment.

There are power, speed, and complexity trade-offs in cache design. Here were a few of them:

Direct-mapping is the simplest approach, and means a given address can only exist in one location, but a problem occurs when two addresses map to the same cache line - one is evicted even if there's plenty of space in the cache elsewhere.

What if we built an associative cache, where every line had an address indicator? Then we can fully use the cache space. But it's far more complicated to search: a miss requires checking every cacheline. If it's fast, so does a hit.

Many systems today use a mix. Smaller caches are often direct mapped. Larger caches tend to use a combination of 2-8 direct-mapped caches where an address can be searched in at the same time, or within a few cycles of each other.

Another problem is evictions becoming a future cache miss. With only a large L1, a cacheline was either in fast L1 or in DRAM. There's often a write buffer or victim cache between them to try to hide dirty eviction latency, but a subsequent fetch will pay the DRAM access cost. As we scale the cache size up, L1 access speed becomes challenging and eventually it's more effective to limit the L1, and build a even larger, slower L2, and then we get the advantage that L2 is still faster than DRAM and we can prefetch into it.

This cache hierarchy tends to fit typical access patterns better as well - for many workloads most accesses will tend to be clumped together. For streaming workloads like video processing that won't fit in a L1 cache anyway, the algorithms are usually aware of row/column/striding impacts on cache utilization already.

There's probably more to consider, like SMP.

by bobmcnamara

4/25/2025 at 12:48:35 AM

PA-RISC clock speeds were relatively low for the time of their introduction. For example, the PA-8900 was launched in May 2005. The low end Athlon 64 of May 2005 was clocked at 2.2GHz (and eventually hit 3.2GHz) versus the PA-RISC top clock of 1.1GHz. You can always build a larger L1 cache in the same process tech if you're willing to sacrifice clock speed sufficiently.

by bcrl

4/23/2025 at 6:39:56 PM

Access time is a a function of areal density, not unlike hard drives. Plus access logic increases at least logarithmic to the number of lines in the cache, so you’re probably looking at in the neighborhood of 50% slower for every doubling of L1 cache size.

Now as to why cache sizes didn’t increase much once clock speeds stagnated and feature size continued to decline, I couldn’t say. But L3 caches didn’t used to exist, and L2 has gotten bigger.

by hinkley

4/23/2025 at 10:47:13 AM

> How far away the memories are in space is way more critical than the speed of any one element in isolation.

Correct me if I'm wrong, but I don't think this is true. If you put instant memory a whole meter away it'll still only have a round trip of 6.6ns at the speed of light, which is approximately the latency of L2. Given how close L2 is, I don't think distance is a large factor of its latency.

by ben-schaaf

4/23/2025 at 11:06:44 AM

The problem is resistance and parasitic capacitance scales with wire length, e^(-t/RC) is going to limit your max frequency.

by davemp

4/23/2025 at 3:38:34 PM

L1 cache has fast access because it is small. If you make it larger, you necessarily make it slower to access.

by jeffbee

4/20/2025 at 1:15:07 AM

> The Dirac channel flash shows a program speed of 400 picoseconds, non-volatile storage and robust endurance over 5.5 × 10^6 cycles.

by thund

4/23/2025 at 6:17:00 AM

So, about 2ms of use? That lifetime seems like this is far from practical as a replacement for SRAM.

by rcxdude

4/23/2025 at 10:37:57 AM

The cycles are programming cycles, not clock cycles. Their stability measurement was 60,000 seconds.

by kryptiskt

4/23/2025 at 7:12:38 AM

Would it be lower power than DRAM?

by jmpman

4/23/2025 at 7:58:39 AM

Yes!

by Tepix

4/23/2025 at 1:36:08 PM

If it's low power you can stack it higher without worrying so much about it melting. This might make a great high capacity cache.

by infogulch

4/23/2025 at 6:25:13 AM

My guess is they are thinking of it more as a replacement for dram or disk. I didn't read far enough to learn if it failed after all those cycles or just "we stopped testing it". Either way it sounds promising.

by dgoldstein0

4/23/2025 at 6:23:45 AM

Can it be used as FPGA config RAM? Also, maybe for faster SSDs?

by codedokode

4/23/2025 at 6:49:34 AM

I think they mean write-read cycles.

by Someone

4/23/2025 at 10:04:45 PM

And then throw in some co-located compute there using chiplets, entirely bypassing the memory bus and PCIe. That'd be _the_ ideal Transformer substrate. Memory bandwidth bottleneck just disappears for the most part. Memory size bottleneck, too.

by ein0p